Buffered inputs and outputs, Fully static operation, Medium-speed operation 100% tested for quiescent current at 20 V, Standardized, symmetrical output characteristics, Common reset 5-V, 10-V, and 15-V parametric ratings, Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C, Noise margin (over full package-temperature range): 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 V at VDD = 15 V Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices", Applications: Control counters Timers Frequency dividers Time-delay circuits The CD4024B are ripple-carry binary counters. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times. All inputs and outputs are buffered.